Integrated circuit chip manufacturers fabricate advanced semiconductor devices by different combinations of processes such as sequentially forming metals, oxides, doped semiconductor and other materials in layers usually thinner than one micrometer (micron) and, then, etching away predetermined portions of the thin layers from the surface of the semiconductor substrate. In these techniques, manufacturing process control and fabrication tolerance are important considerations. Moreover, as the integrated circuit packing density and chip size increase with each new technology generation, ensuring process control and satisfying fabrication tolerances become even more important requirements. Many conventional fabrication techniques and device structures, however, cannot easily meet these requirements.
One important aspect of forming semiconductor devices is the ability to electrically isolate each active component from other active components on the integrated circuit. While this is a critical consideration in Very-Large-Scale Integrated (VLSI) circuits and Ultra-Large-Scale Integrated (ULSI) circuits, traditional isolation structures are not easily scalable for use in sub-half micron VLSI and ULSI technologies. There are numerous reasons why the conventional isolation techniques have not proven scalable down to the sub-half micron regimes. For example, the widely used isolation method known as local oxidation of silicon (LOCOs) is an isolation technique used to form isolation structures in integrated circuit devices. The LOCOs isolation, however, suffers from a limitation know as formation of what is often called "bird's beak" regions at the isolation edge regions of active regions of the devices which limits the minimum spacing between active regions of integrated circuit devices, increasing the minimum spacing.
Trench isolation is often used to isolate the active regions of integrated circuit devices. Isolation trenches are etched into field regions which extend between active regions of the integrated circuits, and then dielectric plugs are formed within the isolation trenches to electrically isolate the active regions. Channel stops may also be formed by implanting dopant impurities into regions of semiconductor substrates which are adjacent to the isolation trenches in which the dielectric plugs are formed. For example, a P+ channel stop may be formed in a P-type substrate by implanting boron. Channel stops increase the effective minimum spacing between the active regions of integrated circuit components by decreasing the effective widths of the active areas.
Isolation trenches are initially formed with sharp, squared edges where the sidewalls of the trench meet the outer surface of the substrates. Squared edges cause two problems. First, squared edges create electric field concentrations such that dielectric breakdown is more likely than if the edge of the trenches were rounded. A second problem is that gate oxide layers are thinned when the squared edges of the isolation trenches are encountered at the edge of a transistor adjacent to the isolation trenches. The gate oxide layers are more likely to breakdown where they are thinned at the squared edges of the isolation trenches.
Current photolithography limits restrict the spacing between active regions which are separated by trench isolation field oxides. Present photolithography limits restrict the minimum size of windows of masking materials, which are deposited on top of substrates to define active regions, to approximately 0.3 microns. Channel stops further increase the effective spacing between active areas by encroaching into the active area, which decreases the effective active area width. Increased minimum spacing requirements result in a reduction of the number of components which may be formed of a single integrated circuit, reducing the effective component width where a preselected number of components are to be formed in a particular region of the integrated circuits.
For bulk silicon integrated circuits with LOCOS isolation, the moat to moat spacing has generally been limited by process and electrical considerations rather than the lithography limits. In contrast, for SOI (Silicon-On-Insulator) integrated circuits with mesa isolation, and more recently for bulk integrated circuits with shallow trench isolation, the moat to moat spacing is approaching lithographic limits. The lithographic equipment and processes to achieve sub-micron dimensions become increasingly expensive, such as deep UV lithography and phase-shift masks. Therefore, there is a need for processes to fabricate moat to moat spacing at dimensions smaller than the limits of the lithographic equipment used. This would allow achievement of moat spacings smaller than the state of the art lithography limits. Alternatively, this would allow the use of less expensive lithographic equipment and procedures for definition of the moat pattern.